The present invention relates to the manufacture of semiconductor integrated circuits and more particularly to an improved method of forming a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer that has a low aspect ratio. Typically, such a composite structure consists of a top silicon nitride (Si3N4) layer, an intermediate refractory metal silicide layer (e.g. WSix) and a bottom doped polycrystalline silicon (polysilicon) layer. The deposition of a refractory metal silicide over a layer of doped polysilicon is extensively used in the semiconductor industry, forming a so-called polycide layer. The above method finds a valuable application in the fabrication of borderless metal contacts.
In the manufacture of such advanced semiconductor IC""s, particularly in dynamic random access memory (DRAM) chips, insulated gate field effect transistors (IGFETs) are extensively used. In a particular implementation commonly found in 16/64 Mbit DRAM chips, each individual memory cell is comprised of an IGFET and a storage capacitor. A composite Si3N4/polycide structure can be found above a silicon substrate coated with a thin SiO2 gate layer to form the gate conductor of the IGFET as known for those skilled in the art. The gate conductor formation which requires the step of etching such a Si3N4 dielectric/polycide structure is essential in the fabrication of the borderless metal contact with a diffusion (source/drain) region of the IGFETs. The borderless metal contact fabrication will be now briefly described by reference to FIGS. 1A-1F.
FIG. 1A schematically shows a portion of a semiconductor wafer at the initial stage of the borderless metal contact fabrication. In FIG. 1A, there is shown a conventional semiconductor structure 10 comprising a silicon substrate 11 coated by a thin 8.5 nm silicon oxide (SiO2) layer 12 (the gate dielectric of the IGFETs) with the gate conductor (GC) stack 13 formed thereon. The GC stack 13 typically consists of a plurality of layers that are superposed: a bottom 150 nm thick arsenic doped polysilicon layer 14, an intermediate 120 nm thick tungsten silicide (WSix) layer 15, and a 410 nm thick silicon nitride (Si3N4) capping layer 16. The Si3N4 capping layer 16 and the combined WSix/doped polysilicon materials of layers 15 and 14 thus form the dielectric/polycide structure mentioned above. Finally, a bottom anti-reflective layer, referred to hereafter as the BARL layer 17 and a photoresist layer 18 terminate the layered structure shown in FIG. 1A. The BARL layer 17 thickness is typically of about 90 nm. As apparent in FIG. 1A, the thickness of stacked layers 14 to 17 is represented by parameter Axe2x80x2.
The GC stack 13 delineation process starts with the patterning of the photoresist layer 18 to produce the desired mask which will subsequently be used to transfer the desired pattern fixed in the resist mask to the underlying layers. To that end, the photoresist layer 18 is exposed, baked and developed as standard. The BARL and the Si3N4 materials of layers 17 and 16 are dry etched in sequence in the same tool. A CF4/CHF3/02/Ar chemistry and an AME P5000 RIE etcher manufactured by Applied Materials, Santa Clara, Calif., USA are adequate for that step. The etch process is monitored through an optical etch end point system as standard.
The etch operating conditions are:
wherein xe2x80x9csccmxe2x80x9d denotes standard cubic centimeters per minute.
The resulting structure is shown in FIG. 1B. Now turning to FIG. 1B, the dimensions of GC stacks and spaces therebetween is represented by C1 and B1 respectively. The dimensions of C1 and B1 are derived from the dimensions Cxe2x80x3 and Bxe2x80x3 of the physical mask used for the resist layer 18 exposition. As further apparent in FIG. 1B, the resist layer 18 lateral profile exhibits typical dimensional swings forming the undulations depicted therein. This defect induces polymer residues on the BARL layer 17 sidewall, which in turn creates a xe2x80x9cfootxe2x80x9d at the base of Si3N4 layer 16.
Now, the BARL layer 17 and the photoresist mask 18 are stripped by ashing in ozone and structure 10 is cleaned as standard.
The next step consists in transferring the pattern into the underlying WSix layer 15 using the remaining part of the Si3N4 capping layer 16, referred to hereinbelow as the Si3N4 cap 16, as an in-situ hard mask. This step is monitored by an optical etch end point system to detect the WSix layer 15/doped polysilicon layer 14 interface. This process uses a C12/HC1/O2 chemistry with a LAM TCP 9400 plasma etcher, an equipment sold by LAM RESEARCH Corp., Fremont, Calif., USA.
The operating conditions are:
Next, the doped polysilicon layer 14 is etched in the same RIE etcher without stopping plasma discharge. The mixture is now reduced to the C12 and O2 compounds. This composition change aims to increase selectivity between doped polysilicon and SiO2 in order to preserve SiO2 gate layer 12 integrity. The etch operating conditions becomes:
This step is monitored by an optical etch end point system to detect the doped polysilicon layer 14 /SiO2 layer 12 interface.
An overetch is performed during a fixed time (60 seconds) in order to eliminate polysilicon residuals without affecting the integrity of the SiO2 material of the thin gate dielectric layer 12. At this stage of the fabrication process, the structure 10 is shown in FIG. 1C. Because the chemistry used to etch the WSix layer 15 is very aggressive, a non negligible part of the Si3N4 cap 16 is consumed during this step. This erosion which is visible in FIG. 1C, reduces the GC stack 13 height which is indicated by reference A1 in FIG. 1C. The wafer is cleaned in a DHF solution as standard to remove the SiOx residuals formed on the SiO2 gate layer 12 and on the GC stack sidewall during the previous etch step in order to adjust the profile topography. As apparent in FIG. 1C. the remaining portions of the GC stack now have the general shape of lines, but are still indicated by reference numeral 13.
The borderless contact to diffusion fabrication process continues with the formation of Si3N4 spacers coating the lateral sides of the GC stacks 13 for sidewall protection. The material deposited has the same nature as the Si3N4 used for capping the GC stacks 13. To that end, a 60 nm thick Si3N4 layer is conformally deposited by low pressure chemical vapor deposition (LPCVD) onto the structure 10 and anisotropically etched in an RIE reactor to form Si3N4 spacers referenced 19 in FIG. 1D. An optical etch end point system is used to detect the SiO2 gate layer 12 exposure as standard. A diffusion (source/drain) region 20 of the IGFET is then formed by ion implantation in desired locations as standard. At this stage of the GC stack fabrication process, the structure is shown in FIG. 1D.
Still referring to FIG. 1D, the Ap parameter which measures the GC stack 13 height is obtained after a succession of processing steps. As a matter of fact, the GC stack initial height Axe2x80x2 is reduced to a value A1 after the WSix layer 15 etching which has caused a significant consumption of the material of Si3N4 cap 16 (due to the use of a non-selective chemistry) and then further reduced to a value Ap because of the overetch of Si3N4 spacer 19. Now, if we consider the Bp parameter which is the width between two GC stacks 13 coated with the Si3N4 spacer 19, it is very dependent on the thickness of spacer 19 and the overetch. Parameter Bp is first determined by parameter Bxe2x80x3 (i.e. the mask design, see FIG. 1B) which becomes B1 after the Si3N4 cap layer 16 and polycide layer 14/15 etching (due to etch bias), and DHF cleaning (with passivation removal). Finally, after Si3N4 spacer 19 fabrication B1 becomes Bp. It is important to point out that the illustrations in the drawings are not necessarily drawn to scale; in reality parameter Ap is usually much greater than parameter Bp.
A 2100 nm thick layer 21 of BPSG is blanket deposited by plasma enhanced chemical vapor deposition (PECVD) onto the FIG. 1D structure 10. The BPSG material forming layer 21 has the double role of an insulating and planarizing medium. However, because the BPSG layer surface is not perfectly planar, a chemical-mechanical polishing (CMP) step is required to get a mirror-like surface and reduce the BPSG layer thickness to 1400 nm. At this stage of the GC stack fabrication process, the resulting structure is shown in FIG. 1E. As apparent in FIG. 1E, the BPSG layer 21 presents a cusp at its top surface between to adjacent GC stacks 13 which is caused by the well-known dishing effect.
A photolithography step is performed in order to define the contact opening locations in a resist mask. Using this mask, the BPSG layer 21 and the SiO2 gate layer 12 are etched in a two-step sequence to expose the silicon substrate 11 at diffusion region 20 locations. The diffusion region 20 may already be in place, or it may be defined, for example, by ion implantation performed after such etch. To that end, a TEL 85 SDRM, a RIE etcher manufactured by TOKYO ELECTRON Ltd, Tokyo, JA is adequate with the operations conditions recited below.
Then, a 25 nm thick dual adhesion layer of titanium/titanium nitride (Ti/TiN) forming a liner is deposited onto the wafer by sputtering. This is followed by the blanket deposition of a tungsten (W) layer by chemical vapor deposition (CVD) to fill contact openings to form metal contacts referenced 22 in FIG. 1F. Next, the wafer is chem-mech polished with an adequate slurry to remove the tungsten and titanium/titanium nitride in excess.
The initial part of forming the GC stack 13 in this borderless metal contact fabrication process which is described by reference to FIGS. 1A-1C is more detailed in the Int. Appl. published under the PCT bearing NO W096/27899. The only noticeable change is that Si3N4 has replaced the SiO2 material as the stack top layer 16. As a matter of fact, Si3N4 is now preferred because it has a higher selectivity than SiO2 with respect to the BPSG material forming layer 21 which is used for the contact opening formation. With the continuous trend towards integration density increase, the BPSG material reveals to be an essential element to reach the small dimensions and/or high aspect ratios that are now required in advanced ICs. In particular, the BPSG materials allows to totally fill the space between two GC stacks 13 without any void, as apparent in FIG. 1E, thanks to its high pouring capability.
Now turning to FIG. 1F, the erosion of the Si3N4 cap 16 produced during the step of etching the WSix material of layer 15 (see FIG. 1C), causes some areas of the remaining portions of this layer to be exposed at locations 23 during the contact opening formation. As a result, there is produced an electrical short between the borderless contact 22 and the WSix material of the GC stack 13 at these locations, making thereby the corresponding IGFETs inoperative.
On the other hand, to perform an electrical contact with diffusion region 20 between two GC stacks 13 and taking into account that Bp parameter (the width between two GC stacks 13 along the X-axis is small compared to Ap parameter (the height of the GC stack 13 along the Y-axis), etch time must be long enough to reach the substrate 11. The longer the etch time becomes, the larger the contact opening becomes and thus, the wider the contact opening becomes at the top of the GC stack 13. As this contact opening becomes higher it induces a significant erosion of Si3N4 cap 16. As a result, the Ap parameter is variable across the wafer due to the topography and in particular above the shallow trench isolation (STI) regions.
Spacer etching and overetch are important because they affect the Al and B1 parameters, and thus the Ap and Bp parameters due to the non-selective etching of the Si3N4 materials of the capping layer 16 and spacer layer 19 which have the same stoichiometry. This lack of selectivity induce mask erosion and reduces Si3N4 cap 16 thickness after spacer 19 formation as mentioned above.
During the photolithography process which defines the desired pattern in photoresist layer 18, standing waves are created along the resist lines, leaving undulations on their lateral sides (see FIG. 1B) which are uncontrollable from wafer to wafer and lot to lot). As a consequence, polymer residuals are produced at the bottom of the BARL lines which in turn cause said xe2x80x9cfootxe2x80x9d at the Si3N4 lines bottoms that are very detrimental to an accurate C1 dimension control.
Ap and Bp parameters defined the aspect ration factor AR such as AR=Ap/Bp. Factor AR is a key feature because at contact opening through the BPSG layer 21 (FIG. 1F), if Ap is much greater than Bp, the contact opening size is widened with a serious risk of electrical shorts between the WSix of layer 15 and the metal contact 22. The challenge is on the Ap parameter because more device integration involves a gate stack height reduction and a requirement to keep Ap as uniform as possible. The Bp parameter is defined by the mask design and the ground rule specifications and finally it determines the width of the GC stack 13, and thus the speed of the IGFETs. To improve process integration for advanced products requires a low aspect ratio factor AR for IGFETs and metal interconnects fabrication. Therefore, these parameters Ap and Bp must obviously be as reproducible as possible.
It is therefore a primary object of the present invention to provide an improved method of fabricating a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer that uses a dielectric sacrificial layer as an in-situ hard mask.
It is another object of the present invention to provide an improved method of fabricating a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer that has a low aspect ratio factor AR with reproducible values across the wafer.
It is another object of the present invention to provide an improved method of fabricating a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer that permits a significant reduction of the structure height and a better dimensional control thereof.
It is another object of the present invention to provide an improved method of fabricating a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer which relies upon the use of a dielectric material that is conformal and impervious to UV radiation.
It is still another object of the present invention to provide an improved method of fabricating a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer wherein the dielectric has an inorganic nature and a stoichiometry close to the Si3N4 material.
It is still another further object of the present invention to provide an improved method of fabricating a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer wherein the dielectric is oxynitride.
It is still another further object of the present invention to provide an improved method of fabricating a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer wherein the dielectric is oxynitride, a material close enough to Si3N4 to allow etching of both materials in the same tool in the same run.
It is still another further object of the present invention to provide an improved method of fabricating a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer wherein the dielectric is oxynitride, a material different enough to be used as an etch stop layer vis a vis the Si3N4 material during Si3N4 spacer formation.
It is still another further object of the present invention to provide an improved method of fabricating a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer that finds a valuable application in the fabrication of borderless metal contacts
According to the present invention there is described a method of fabricating a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer having a low aspect ratio comprising the steps of:
a) providing a structure consisting of a silicon substrate coated with a bottom thin SiO2 layer, a doped polysilicon layer, a refractory metal layer and a top Si3N4 capping layer; said refractory metal and doped polysilicon layers forming a polycide layer under subsequent thermal treatments;
b) depositing a sacrificial layer of a dielectric material onto the structure, said dielectric material being impervious to UV radiation and having a good conformal property;
c) depositing a layer of a photoresist material onto the structure;
d) patterning said photoresist layer to form a mask;
e) anisotropically dry etching the dielectric and top Si3N4 layers using the photoresist mask;
f) stripping the photoresist mask;
g) anisotropically dry etching the refractory metal and doped polysilicon layers down to the SiO2 layer using the patterned dielectric layer as an in-situ hard mask;
h) depositing a conformal layer of Si3N4, referred to as the Si3N4 spacer layer, onto the structure;
i) anisotropically dry etching the Si3N4 spacer layer until the thin SiO2 layer is exposed to form the Si3N4 spacers;
j) ion implanting dopants into the silicon substrate to create diffusion regions at desired locations;
k) depositing a layer of boro-phospho-silicate-glass (BPSG) onto the structure and planarizing it;
l) forming contact holes to expose said diffusion regions; and,
m) filling said contact holes with a metal to create metal contacts with the diffusion regions.
The oxynitride (SixOyNz) material provides an anti-reflective coating which has the property of lowering the composite Si3N4/polycide structure aspect ratio factor and of improving the dimensional control (CD) thereof all across the wafer with a high reproducibility. As a result, electrical shorts related problems of the conventional borderless metal contact fabrication process are eliminated.